1. Field of the Invention
The present invention relates to a multi-layer wiring board, to a semiconductor package, and to a method of manufacturing the multi-layer wiring board.
2. Description of the Related Art
In recent years, there has been developed, as a semiconductor device such a semiconductor large scale integrated circuit (LSI), one whose operating speed is increased up to 1 GHz in terms of clock frequency. In such a high-speed semiconductor device, the integration degree of transistors is fairly high, so that the number of input/output terminals may in sometimes exceed over 1,000.
In order to mount such a multi-terminal semiconductor device on a printed wiring board, there have been developed various kinds of techniques. The techniques which are currently widely put into practical use include an interposer such as BGA (Ball Grid Array) and CSP (Chip Size Package).
FIG. 1 illustrates one example of an IC package wherein a semiconductor device is mounted on an interposer of BGA structure and packaged in a printed wiring board.
Referring to FIG. 1, a multi-layer circuit wiring board 53 comprises a copper-clad substrate (glass epoxy substrate) 530 made from glass cloth into which epoxy resin is impregnated, a first layer 531 formed of a laminate comprising insulating layers and conductive wiring layers, which are alternately superimposed, and a second layer 532 formed of a laminate also comprising insulating layers and conductive wiring layers, which are alternately superimposed. The first layer 531 is placed on one of the main surfaces of the glass epoxy substrate 530, and the second layer 532 is placed on the other main surface of the glass epoxy substrate 530.
The first layer 531 is provided on the top surface thereof with surface-treated gold pads 536, and with gold bumps 537 for bringing into contact with the electrodes (not shown) of a semiconductor device 54. Further, the second layer 532 is provided on the bottom surface thereof with surface-treated gold pads 538 for bringing into contact, through a solder ball 52, with a conductive wiring layer 511 of a printed wiring board 51. A pad 536 is electrically connected with a pad 538 by way of via-contact conductor layers 533 and 535.
A method of forming a multi-layer circuit wiring board by successively piling up insulating resin layers and conductive wiring layers one upon another on a glass epoxy substrate as described above is called a build-up technique. Details of this technique are described for example in Japanese Laid-open Patent Publication (Kokai) No. 4-148590 (1992).
In this technique, it is no longer required to employ a core material such as glass cloth which has been conventionally employed as an insulating layer of a multi-layer circuit wiring board and laminated together with a wiring layer. Namely, the insulating layer of the multi-layer circuit wiring board is formed in this technique by a method wherein a photosensitive resin composition is coated on a surface of glass epoxy substrate and then cured to form the insulating layer. On the other hand, the wiring pattern of the multi-layer circuit wiring board according to the aforementioned build-up technique is formed by making use of a plating method in contrast to that of the conventional multi-layer circuit wiring board. Therefore, it is possible, according to the aforementioned build-up technique, to form a finer wiring pattern in the multi-layer circuit wiring board as compared with the wiring pattern of the conventional multi-layer circuit wiring board. For example, it is possible to form a wiring pattern 50 μm in line width and about 50 μm in width of space between lines.
The via-contact layer 535 for bringing into contact with both of upper and lower conductive wiring layers can be formed by a method wherein a fine hole is formed in the layer by means of photolithography by taking advantage of the photosensitivity of a resin composition, and then the hole is filled with a conductive material by means of plating. In the case of the conventional multi-layer circuit wiring board where all of the layers are collectively laminated, the diameter of the through-hole cannot be made smaller than 300 μm. Whereas, according to the aforementioned build-up technique, the diameter of the through-hole can be made as small as 100 μm or so, thereby making it possible to enhance the density of the through-holes.
However, the structure of the conventional multi-layer circuit wiring board is accompanied with the following problems in enhancing the density of wirings, in increasing the transmitting speed of signals, and in promoting the mass production thereof.
First, the conductive wiring layer according to the build-up technique is formed at first by way of electroless plating on an insulating resin layer, which is followed by electrolytic plating. Generally, the adhesive strength of the electroless-plated layer to the insulating resin layer is relatively low. Therefore, the surface of the insulating resin layer is roughened prior to the electroless plating to have a surface roughness 5 μm to 10 μm in maximum height, thereby promoting the anchoring effect and hence enhancing the adhesive strength of the electroless-plated layer. Due to this surface roughness however, non-uniformity in lateral direction is caused to generate on the occasion of forming a wiring pattern by an etching method, etc., thereby making it impossible to obtain a wiring pattern excellent in linearity. In a wiring pattern where the line width thereof is 50 μm or less, this non-uniformity cannot be disregarded. Namely, noise due to reflection may become enlarged on the occasion of passing signals at a high speed, thus raising a problem. Therefore, according to the conventional build-up technique, it is difficult to manufacture a multi-layer circuit wiring board which is high in density of wiring pattern and capable of transmitting signals at a high speed, or more specifically, a multi-layer circuit wiring board having a fine wiring pattern 50 μm or less in line-and-space, and hence to manufacture an IC package having such features.
Secondly, since the glass epoxy substrate is poor in flexibility, it is impossible to adopt a roll-to-roll technique which is designed to continuously manufacture a multi-layer circuit wiring board by making use of a long strip of base material, and hence it is difficult to apply a mass-production method to the manufacture of the conventional multi-layer circuit wiring board.
Thirdly, as described above, as a semiconductor device is designed so as to further increase the processing speed thereof, the number of input/output terminals of the semiconductor device is also required to be proportionally increased. Under such circumstances, the conventional wire bonding method is no longer capable of performing the electrical connection between such an increased number of terminals and the interposers. On the other hand, the wirings extending from the connecting terminals which are provided within the interposer can be hardly dealt with by a single layer and hence may be required to be separated so as to arrange them in at least two layers. Further, in order to cope with the speedup of signals, it may be required to adopt a microstrip structure of wirings, a strip structure of wirings, or the multiplication of wirings such as a coplanar structure.
However, as far as the manufacturer of the interposer is concerned, any increase in number of wiring layers leads to a substantial reduction of yield. Therefore, it is very important to consider how to effectively arrange the wirings, and how to design the wirings in order to minimize the number of wiring layers. There are increasing demands for the development of a multi-layer circuit wiring board and an IC package where the wirings thereof are constituted by a wiring pattern of finer line-and-space in order to realize an effective arrangement of wirings.
Fourthly, as described above, in the multi-layer circuit wiring board to be according to the build-up technique, a substrate (glass epoxy substrate) manufactured by means of the conventional method is employed as a core layer of the wiring board. In order to electrically connect the upper side of the substrate with the underside side thereof, a through-hole is formed by making use of a drill, and plating is applied to the inner wall of the through-hole to thereby obtain a plated through-hole. In this case, since the through-hole is mechanically formed by making use of a drill, the miniaturization in size of the through-hole would be considerably restricted. Likewise, for the same reason, the minimization in pitch of the through-holes would be considerably restricted. For example, at present, a typical value of the diameter of the through-hole is 300 μm, and a typical value of the pitch of the through-holes is 800 μm.
As described above, since the miniaturization in size of the through-hole as well as the minimization in pitch of the through-holes are restricted, there is a problem in the prior art that the density of BGA ball pin cannot be enhanced. As a result, any increase in the number of input/output terminals in a semiconductor device would inevitably lead to an increase in size of the body of the interposer, resulting in the elongation in length of the wirings and hence in the delay of signals.
Additionally, since the pitch of the through-holes in the core layer is relatively large, a high density fine wiring is formed only on one of the build-up layers which is designed to mount semiconductor devices. Whereas, the other build-up layer which is disposed on the opposite surface of the core layer and designed to mount balls is frequently employed solely for preventing the warpage of the wiring board. As a result, the number of layers is caused to increase more than needed, which leads to an increase in manufacturing cost of the wiring board.
Further, since the glass epoxy substrate to be employed as the core layer is generally made of a glass cloth, the thickness of the core layer becomes relatively large, thus substantially increasing the total thickness of the interposer. If the total thickness of the interposer is increased in this manner, it becomes difficult to align the characteristic impedance of the wirings formed in board-thickness direction, i.e. the through-hole and via-contact layer, thus making it disadvantageous in enhancing the operating speed of semiconductor device.
The present invention has been accomplished in view of overcoming the aforementioned problems, and therefore, the objects of the present invention are to provide a method of manufacturing a multi-layer circuit wiring board, which is capable of forming a wiring pattern having a fine line-and-space, and of adopting a roll-to-roll technique where a long strip of base material is employed to continuously manufacture a multi-layer circuit wiring board.